Power delivery network (PDN) design is critical for providing clean power to integrated circuits, such as field-programmable gate arrays (FPGAs) and other electronic devices. A high percentage of the area of a printed circuit board (PCB) and system board costs are dedicated to the several PDNs that are typically found on product PCBs. Optimization of printed circuit board designs strive to provide the cleanest power possible without over designing the PCB with extraneous decoupling capacitors, which are not effective and unnecessarily add cost. To achieve effective PCB designs during the early design phase without going through extensive pre-layout simulations, board designers must accurately estimate the number, the capacitor values, and the type of decoupling capacitors.
One type of decoupling capacitor tool simply calculates the impedance of the PDN as a parallel combination of many decoupling capacitors. This method of impedance calculation is sometimes called single node analysis because all the capacitors are in parallel and attached between a single power supply node and ground. Typical usage of single node analysis has been to choose a number of decoupling capacitors required to meet a target impedance up to an arbitrary frequency. A significant shortcoming of single node analysis is the lack of information regarding other sources contributing to the impedance of the power delivery network, such as the spreading inductance of the power and ground planes and the inability to judge how changes to the PCB configuration will affect the PDN impedance.
Another type of decoupling capacitor tool provides the extracted impedance of the PDN but does not give any guidance into the number of capacitors that may be effective or the limiting factors of the PCB that render the capacitors ineffective. This type of tool uses multi-node analysis, which is heavily computer-resource intensive. The usefulness of multi-node analysis is limited due to the requirement of having extensive post-layout information in order to get accurate results. In addition, the resource intensive nature of multi-node analysis prevents its use in instances where a designer desires to quickly investigate different options for PCB configurations.
It is in this context that embodiments of the invention arise.